The present invention relates to an improved comparator circuit for use in an analog-to-digital conversion circuit apparatus or the like.
Heretofore, in the case of fabricating an A/D converter for converting an analog signal having a video frequency band of approximately 6 MHz into a digital signal using CMOS, there has been known a parallel A/D converter including comparators which compare reference voltages of the number corresponding to the resolution of the A/D converter with analog input signals, and also a serial-parallel A/D converter which classifies digital data into a higher rank and a lower rank for conversion, as a result of which the number of comparators is remarkably reduced in comparison with the parallel A/D converter. Among the converters of this type, in an A/D converter having the resolution of 8 bits or more, an analog/digital hybrid semiconductor integrated circuit device is known in which an A/D converter and a digital signal processing circuit are formed into one chip package, and the like, and because such devices are largely affected by noise from a power source, most frequently used are differential chopper type comparator circuits which use differential amplifier circuits providing strong protection against noise from the power source and remarkably which reduce offset voltage which otherwise causes a problem in a CMOS differential amplifier circuit, for example, as shown in FIG. 2A.
In FIG. 2A, analog switches 11, 12, 31, 32, 41, 42, 51 and 52 are controlled by control signals .PHI..sub.S1, .PHI..sub.S, .PHI..sub.C and .PHI..sub.S3, respectively, and the respective control signals are applied to the analog switches of comparator circuits shown FIG. 2A in accordance with timing charts shown in FIG. 2B.
In the case where the control signals are applied to an example of the conventional comparator circuit shown in FIG. 2A in accordance with the timing charts of FIG. 2B, the circuit operates in the following manner, assuming that C1 and C1' are equal to each other, and C2 and C2' are also equal to each other in capacitance.
(1) When each of .PHI..sub.S, .PHI..sub.S1 and .PHI..sub.S3 is at a "H" level and .PHI..sub.C is at a "L" level, one end of capacitors C1 and C1' are applied with input voltages V1 and V3 by the operation of the switches 31 and 32, respectively. Differential amplifier circuits 10 and 20 have input and output terminals which are opposite in phase and short-circuited by the switch circuits 11 and 12 and by the switch circuits 51, 52, respectively. In the differential amplifier circuit 10, an input terminal 1 and an output terminal 3 are connected to each other through the switch circuit 11 whereas an input terminal 2 and an output terminal 4 are connected to each other through the switch circuit 12. In the case where the differential amplifier circuit is formed of a CMOS construction, because circuits shown in FIGS. 3 and 4 are used as the differential amplifier circuit, the input and output voltages of the differential amplifier circuit become constant values determined by the circuit.
(2) When .PHI..sub.S1 becomes "L" earlier than .PHI..sub.S and .PHI..sub.S3, the switch circuits 11 and 12, which have allowed the input and output terminals of the differential amplifier circuit 10 to be short-circuited, are opened. At this time, since .PHI..sub.S still remains "H", if a time until .PHI..sub.S is thereafter opened is satisfactorily short in comparison with the change of an analog input signal, the change from the input side is ignored. However, the noise from the control signal caused by opening the switch circuits 11 and 12, that is, clock field through-noises are added to the two input terminals 1 and 2 of the differential amplifier circuit 10 in phase. Since a difference between voltages applied to both ends of the switch circuits 11 and 12 when the respective switch circuits are opened is slight, the clock field through-noises applied to the two input terminals of the differential amplifier circuit 10 are in phase and at the same level, and influence of the clock field through-noises on the circuit characteristics of the comparator can be ignored by the in-phase removing characteristics of the differential amplifier circuit.
(3) Subsequently, when .PHI..sub.S and .PHI..sub.S3 become "L", the input voltages V1 and V3 are cut off from the capacitors C1 and C1', and the differential amplifier circuit 20 is placed in an operating state by opening the switch circuits 51 and 52 which have allowed the input and output terminals of the circuit 20 to be short-circuited. The clock field through-noises applied to the two input terminals of the differential amplifier circuit 20 are in phase and at the same level, and therefore their influence can be ignored similarly as in the case where .PHI..sub.S1 becomes "L". However, although the clock field through-noises caused by opening .PHI..sub.S are in phase, if the voltage levels of the input voltages V1 and V3 are different, then the noise levels are also different.. Therefore, the influence of the clock field through-noises cannot be ignored. Because the differential amplifier circuits 10 and 20 are in the operating state, the clock field through-noises are inputted to the two differential amplifier circuits so as to be amplified and then ouputted.
(4) When .PHI..sub.C becomes "H" and the switch circuits 41 and 42 are closed, one respective end of the capacitors C1 and C1' is applied with the analog input voltages V2 and V4. Since the difference between voltages applied to both ends of the capacitors is not changed, an output signal of the differential amplifier circuit 10 is represented by: EQU V.sub.out =A(V1=V2-V3+V4)
Therefore, the circuit 10 operates as a comparator.
In the example of the conventional comparator circuit shown in FIG. 2A, when the analog switches 11, 12, 31, 32, 51 and 52 are closed, the analog input signals V1 and V3 are stored in the capacitors C1 and C1'. Then, after the analog switches 11 and 12 are opened so that the input terminal of the differential amplifier circuit 10 is opened and is placed in the operating state, the analog switches 31, 32, 51 and 52 are opened thereby to finish the sampling of the analog input signals. The clock field through-noises from the analog switches 11, 12, 51 and 52 are in phase and at the same level, and therefore there arises no problem because of the in-phase removing characteristics of the differential amplifier circuit 10. However, because the clock field through-noises from the analog switches 31 and 32 are in phase but different in noise level, the clock field through-noises are amplified by the differential amplifier circuit 10 which is in the operable state and further amplified by the differential amplifier circuit 20 when a reaction speed is high or a time interval from a time of sampling the analog input signal to a time of starting a comparing operation is long, as in the comparator used in the A/D converter having the video frequency band. For that reason, in the worst case, there rise such problems that the clock field through-noises exceed the linear operating region of the input and output of the differential amplifier circuits, as the result of which the electric charges stored in the capacitors C2 and C2' are lost, or whereby the differential amplifier circuits are inoperable as a comparator, or that the output signals of the differential amplifier circuits 10 and 20 are saturated immediately before the comparing operation starts thereby delaying the operation speed.